1. Field
One or more embodiments of the present disclosure relate to a hardware structure of an image signal processor (ISP), and more particularly, to a structure and an operation method of a memory installed within the ISP to store line data, for example, a Static Random Access Memory (SRAM).
2. Description of the Related Art
Many functions may be performed by an image signal processor (ISP). For example, the functions may include bad pixel replacement, red, green, blue (RGB) interpolation, noise reduction, edge enhancement, and the like.
Since each of the functions deals with a two-dimensional (2D) image, image data corresponding to some line amounts may be temporarily stored in a memory. For example, when a 3×3 bilinear interpolation is performed, a 3×3 kernel may be used. Therefore, in addition to a current line, two lines prior to the current line may be stored in the memory.
However, most of hardwired ISP costs may be used for a Static Random Access Memory (SRAM). ISPs are used more and more to process high resolution images and an amount of required SRAM may increase proportionally with an increase in image resolution.
Accordingly, there is a desire for a method that may reduce costs used for the SRAM within the ISP, that is, a silicon area.